1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a pattern configuration of a semiconductor device with a plurality of gate electrodes formed on a transistor forming region and arranged in one direction.
2. Description of the Background Art
Generally in designing a semiconductor integrated circuit within a semiconductor device, the entire semiconductor integrated circuit is not constructed at one time. Rather, a number of functional blocks, called standard cells, are combined under a prescribed rule to construct the semiconductor integrated circuit. Such method of combining a plurality of standard cells is called xe2x80x9ccell-based designxe2x80x9d.
The semiconductor integrated circuits of such cell-based design consisting of standard cells include a wide variety of circuits, from basic gate circuits with simple structures, such as inverter circuits, AND circuits and NAND circuits, more complex ones like flip-flop circuits, to relatively large sized block circuits like adders and so on, which are utilized as necessary.
As a rule of the cell-based design, unification in heights of standard cells, thicknesses of power supply lines, locations of wiring and input/output pins and others is attempted so as to place neighboring standard cells at a shortest possible distance from each other. As such standard cells, the one having a layout pattern as shown in FIG. 13, for example, has been utilized.
FIG. 13 schematically shows an underlying structure of a transistor portion in a conventional standard cell. A cell frame 21 delimited by a two-dotted, dashed line represents the standard cell region. This standard cell is provided with gate electrodes 1, 2, 3 and 4 arranged in a gate length direction, and active regions 5, 6 and 7 formed by introducing impurity ions into a silicon substrate by ion implantation.
Gate electrodes 1-4 run across and extend beyond active regions 5-7. Interconnection portions 15, 16, 17 and 18 in prescribed shapes are each provided at either end in a gate width direction of respective one of gate electrodes 1-4.
Regions bounded by active regions 5-7 and gate electrodes 1-4 define source/drain regions 8-14 of transistors. For example, a transistor with gate electrode 1 has source/drain regions 8, 9. A transistor with gate electrode 2 has source/drain regions 9, 10. These two transistors share source/drain region 9. Further, a transistor having gate electrode 3 is provided with source/drain regions 11, 12. A transistor having gate electrode 4 is provided with source/drain regions 13, 14.
Interconnection portions 15-18 are provided so as to electrically connect gate electrodes 1-4 to interconnections (not shown) which are to be placed in a layer overlying gate electrodes 1-4. Normally, contact holes for connection between these interconnection portions and the interconnections in the upper layer are provided, so that gate electrodes 1-4 and the upper-layer interconnections are connected. Likewise, source/drain regions 8-14 are connected to the upper-layer interconnections by providing contact holes in those regions.
Thus, the gate electrode and the source/drain regions of each transistor are electrically connected to the interconnections in the upper layer, so that a logic circuit is constructed. Here, because of the configuration of the standard cell as described above, the size of the transistors can be set arbitrarily by changing the dimensions in the gate width direction of active regions 5-7 and gate electrodes 1-4. As a result, it is readily possible to optimize the performance of the semiconductor integrated circuit.
On the contrary, in a so-called gate array structure, a basic size of transistor is predetermined, and the transistor size is only adjusted by an integer multiple thereof. This makes it difficult to optimize the circuit. Therefore, the cell-based design has an advantage that it can implement LSI (large-scale integration) exhibiting higher performance than in the gate array design.
In recent years, however, miniaturization of elements and interconnections has been drastically advanced and the pattern dimension has become smaller than the wavelength of light source of an exposure system. This causes variation in finished dimension of a pattern after exposure, which now is an innegligible problem. Specifically, in the case of exposure of a regular pattern, elements can be finished in approximately the same size. However, in the case of exposure of an irregular pattern for, e.g., the conventional gate electrodes as shown in FIG. 13, irregular interference of exposure light radiated from the exposure system will result in gate electrodes with their finished dimensions varying from one another.
Taking notice of gate electrode 2 in FIG. 13, for example, it is about twice the length of gate electrode 1 residing on its left side. In other words, gate electrode 1 extends along gate electrode 2 only half the way. In this case, finished dimension of gate electrode 2 in a portion adjacent to gate electrode 1 will differ from that in the remaining portion. Generally in a gate electrode, the gate length determines the performance of the transistor. If the gate length is longer than a designed value, load driving capability during an ON state of the transistor will decrease, thereby degrading the driving speed of the transistor. Conversely, if the gate length is shorter than the designed value, a leakage current during an OFF state of the transistor will increase, thereby increasing the power consumption.
As described above, in the case of cell-based design, if gate electrodes have an irregular pattern, their finished dimensions will vary from one another. This leads to performance degradation, such as a slower operating speed, increased power consumption and the like, of transistors within the semiconductor integrated circuit.
The present invention is directed to solve the above-described problems. An object of the present invention is to provide a semiconductor device having a pattern structure that can suppress performance degradation of transistors.
The semiconductor device according to the present invention includes: a transistor forming region having a plurality of source/drain regions formed on a semiconductor substrate and a plurality of gate electrodes arranged in a first direction, each having a gate width direction that matches a second direction orthogonal to the first direction; and a plurality of field effect transistors each formed of one of the plurality of gate electrodes and two of the plurality of source/drain regions. The plurality of field effect transistors include at least two kinds of such field effect transistors that are different in active region widths corresponding to lengths of the plurality of source/drain regions along the second direction. Each of the plurality of gate electrodes is made to have a gate width that is greater than the longest active region width.
As the gate width of each gate electrode is made greater than the longest active region width as described above, it is ensured that every couple of gate electrodes adjacent to each other have their sides facing with each other within the active region width. Thus, adverse effects of irregular interference of the exposure light can be suppressed, so that it becomes possible to equalize the finished dimension of each gate electrode.
As a preferred embodiment of the present invention, each of the plurality of gate electrodes is provided such that every distance between opposing sidewalls of two adjacent gate electrodes is approximately equal to each other. Still preferably, the plurality of gate electrodes have the same gate length.
With such a configuration, gate electrodes approximately in identical shapes are arranged regularly in the first direction. Thus, at the exposure step in the pattern formation of the gate electrodes, adjacent gate electrode patterns come to affect to each other in an equal manner, so that it becomes possible to obtain an equal finished dimension for every gate electrode. As a result, each gate electrode is fabricated in the same shape, so that the semiconductor device can attain and exert characteristics as designed.
As a still preferred embodiment of the present invention, the semiconductor device includes a plurality of transistor forming regions, which are arranged side by side in the second direction.
Even when multiple transistor forming regions are arranged in the second direction, each gate electrode in each transistor forming region is made the same in shape, so that it becomes possible to allow the semiconductor device to realize characteristics as designed.
As another preferred embodiment of the present invention, the semiconductor device includes a plurality of transistor forming regions, which are arranged in the first direction. A first auxiliary pattern electrode is provided between the transistor forming regions. The first auxiliary pattern electrode is made to have the same gate length as the gate electrodes in the transistor forming regions. It is also placed such that a respective distance between the first auxiliary pattern electrode and each of the closest gate electrodes in the respective transistor forming regions is made equal to a pitch in which the gate electrodes in the transistor forming regions are arranged in the gate length direction. Respective ends in the gate width direction of the first auxiliary pattern electrode are made to align with or extend beyond the respective ends of the gate electrodes in the second direction.
As described above, in the case where the transistor forming regions are arranged side by side in the first direction, the first auxiliary pattern electrode almost in the same shape as each gate electrode is provided between the transistor forming regions in the same pitch as the gate electrodes. Thus, all the gate electrodes are arranged regularly in the first direction. Accordingly, at the exposure step in the pattern formation of the gate electrodes, adjacent gate electrodes come to affect to each other in an equal manner, which results in equal finished dimension of each gate electrode. As a result, each gate electrode is fabricated in the same shape, so that it becomes possible to allow the semiconductor device to realize characteristics as designed.
Further, as a preferred embodiment of the present invention, a second auxiliary pattern electrode is provided outside the outermost gate electrode in the transistor forming region at its side not facing another transistor forming region. The second auxiliary pattern electrode is made to have the same gate length as the gate electrodes, and arranged in the same pitch as the gate electrodes in the first direction. Respective ends of the second auxiliary pattern electrode in the second direction are made to align with or extend beyond the respective ends of the gate electrodes in the second direction.
Thus, the second auxiliary pattern electrode is provide outside the transistor forming region on its side not facing another transistor forming region. Accordingly, at the time of exposure in the pattern formation, conditions are made equal for the gate electrode that is located at the outermost part of the region and for the gate electrode that is located in the center of the region. Thus, it becomes possible to equalize the finished dimension of every gate electrode. As a result, the gate electrodes are all fabricated in the same shape, so that the semiconductor device is able to attain and exert characteristics as designed.
Further, as a preferred embodiment of the present invention, a gate interconnection portion in an arbitrary shape is provided at an end in the second direction of a selected gate electrode.
Still preferably, the plurality of gate electrodes include at least one electrically independent gate electrode, and the remaining gate electrode is provided with the interconnection portion connected thereto which has a width in the first direction that is greater than that of the gate electrode.
As a still preferred embodiment of the present invention, the gate electrodes within the transistor forming region include a first gate electrode that contributes to an operation of the semiconductor device, and a second gate electrode that does not contribute to the operation of the semiconductor device.
Thus, by mixing the first and second gate electrodes, at the exposure step in the pattern formation of the gate electrodes, the adjacent gate electrodes come to affect to each other in an equal manner. Thus, it becomes possible to equalize the finished dimension of every gate electrode. As a result, the gate electrodes are fabricated in the same shape, so that the semiconductor device is allowed to realize characteristics as designed.
Further, as a preferred embodiment of the present invention, a selected gate electrode is formed of a single member from its one end to the other end in the second direction. Still further, a selected gate electrode is divided into at least two parts in the second direction. Even when such configurations are employed, gate electrodes approximately in the same shape can be fabricated. Thus, it becomes possible to bring out from the semiconductor device the characteristics as designed.
As a still preferred embodiment of the present invention, every distance between opposing sidewalls of two adjacent gate electrodes is made the same.
With such a configuration, at the exposure step in the pattern formation of the gate electrodes, it becomes possible to equalize the effects of opposing sidewalls of the adjacent gate electrodes being given to each other. Thus, each gate electrode is fabricated with finished dimension as designed. As a result, the semiconductor device that can bring out characteristics as designed is realized.
As a preferred embodiment of the present invention, the active regions are provided such that every distance between two adjacent active regions in the first direction becomes the same.
With such a configuration, at the time of exposure in the pattern formation of the active regions, it becomes possible to equalize the effects of the adjacent active regions being given to each other. Each active region can thus be fabricated with a finished dimension as designed. As a result, the semiconductor device that can bring out characteristics as designed is realized.
Further, as a preferred embodiment of the present invention, one such transistor forming region is formed in a standard cell.
According to another aspect of the semiconductor device of the present invention, a plurality of the semiconductor devices as described above are arranged in rows and columns to construct a semiconductor integrated circuit. Therefore, it becomes possible to realize a semiconductor device with excellent reliability in its operating characteristics.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.